Supermicro to integrate SambaNova SN50 RDUs into GPU inference racks

Supermicro and SambaNova have agreed to build hybrid AI inference racks combining NVIDIA GPUs with SambaNova’s SN50 Reconfigurable Dataflow Units (RDUs), with Supermicro planning an initial rollout of around 10,000 chips. The architectures target large language model workloads by splitting tasks: GPUs handle prompt prefill processing while SN50 chips execute response token decoding.

Splitting workloads to preserve existing GPU assets

Under the agreement, Supermicro will integrate, test, and support the systems through its building-block catalogue. The design aims to address memory-bound bottlenecks in token generation without requiring hyper-dense, direct-to-chip liquid cooling. SambaNova states its air-cooled chassis packs 16 accelerators per rack, making 10,000 chips equivalent to roughly 625 racks. For system integrators and secondary market brokers, this approach highlights a shifting design pattern in high-density data centres. Rather than replacing older host hardware entirely, data centre operators can retain existing enterprise GPUs for initial prompt compute while offloading sustained output processing to specialised accelerators. This offload strategy allows cloud providers and enterprise buyers to add inference capacity within existing facility power limits.

Market impact for system integrators and resellers

The rollout will initially target neo-clouds and sovereign cloud providers before expanding to on-premises enterprise environments. While neither firm has disclosed firm purchase commitments or exact ship dates, SambaNova expects deployment volumes to step up in 2027 following its recent $1 billion funding round. Single-vendor delivery through Supermicro servers simplifies procurement for trade buyers who want turn-key architectures rather than assembling heterogeneous hardware themselves. For trade buyers and resellers, this points toward a broader trend:

• Mixed-architecture racks are moving from custom hyperscale builds into standard catalogue options.
• Demand for standalone compute nodes may shift as specialised decode processors take over steady-state inference.
• Maintenance providers must prepare for heterogeneous rack layouts requiring distinct support paths for host node components and specialised accelerator chassis.

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